Phase locked loop circuits are old and well known. Typically these circuits include analog phase comparators which achieve phase locking when the reference signal returns after having been interrupted for some period of time. These circuits cause severe local clock frequency disturbances during the phase locking process.
A circuit which does operate to minimize this local clock frequency disturbance is disclosed in U.S. Pat. No. 4,305,045 issued to R. Metz et al on Dec. 8, 1981. In this circuit, the microprocessor which performs the phase comparison, determines the amount of random phase shift which has occured. Then it calculates a five bit word, based on that phase shift, which is used to correct the phase shift. This five bit word is applied to a five bit register which is extensively interconnected with a counter chain which counts down the reference signal.
The five bit word generated by the microprocessor, acts via the register and counter chain circuitry, and dynamically alters the phase of the counted down reference signal to minimize the phase difference between the counted down local and reference signals. However, in this arrangement, complex circuitry and microprocessor calculations are required to perform the phase minimization.